One of the standard fabrication processes for making MOS integrated circuit devices utilizes a self-aligning gate process when forming the associated source and drain regions. This process, which is disclosed in U.S. Pat. No. 3,472,712 which issued Oct. 14, 1969 to Bower, includes the formation of a thin layer of electrically insulating gate oxide on the planar surface of a semiconductor body, the formation of a gate on the insulating material, and the selective implanting of a doping impurity thereby informing the source and drain regions using the gate itself as a mask. After forming the source and drain regions and adding a layer of nitride and a layer of borophosphosilicate glass (BPSG), a two step masking opeation is performed to form the contact openings. The first masking step forms openings through the BPSG. The second masking step extends the openings through the nitride and gate oxide layers so that the surface of the semiconductor body is exposed. The two step masking process is a standard one for many manufacturers because it greatly reduces the chance occurrence of a short due to the presence of foreign matter on the photolithographic plate during the masking process.
In self-aligning gate processes, there is no heavy doping under the gate. Therefore, a capacitor having a dielectric formed of this material is necessarily non-linear. In such processes where a capacitor is formed along with a transistor, the capacitor typically includes a lightly doped substrate electrode and an upper polysilicon electrode. Because the lightly doped substrate electrode can be depleted by the voltage on the upper polysilicon electrode, the capacitor is highly nonlinear and the effective electrical separation between the electrodes is not constant. This renders the capacitor unsuitable for precision measurement applications such as analog to digital converters.
When including a matched capacitor in the structure of a linear CMOS device of either the silicon on insulator(SOI) type, or bulk silicon type, the standard fabrication process must be modified to include an extra mask step and an extra diffusion. That is, the substrate electrode, or capacitor plate, must be heavily doped prior to forming the upper polysilicon electrode which is formed at the same time the gate is formed. On the other hand, when dealing with a CMOS device of the bulk silicon type, the standard fabrication process may be modified somewhat differently. In this case the two plates of the capacitor are formed of polysilicon and have a thin layer of oxide interposed between them. The structure is arranged on an area of isoplanar silicon dioxide. In this case the standard fabrication process must include an additional step to form a second layer of polysilicon and the associated photoresist mask.
What is needed is a method of forming a linear capacitor having high capacitance per unit area utilizing the standard fabrication process without the need for additional process steps. The present invention achieves this by taking advantage of the existing procedure whereby two separate mask steps are used to form the contact openings of the transistor.